32 lines
531 B
Verilog
32 lines
531 B
Verilog
module top(
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input [63:0] key,
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output lock
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);
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reg [63:0] tmp1, tmp2, tmp3, tmp4;
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// Stage 1
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always @(*) begin
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tmp1 = key & 64'hF0F0F0F0F0F0F0F0;
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end
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// Stage 2
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always @(*) begin
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tmp2 = tmp1 <<< 5;
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end
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// Stage 3
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always @(*) begin
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tmp3 = tmp2 ^ "HACKERS!";
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end
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// Stage 4
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always @(*) begin
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tmp4 = tmp3 - 12345678;
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end
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// I have the feeling "lock" should be 1'b1
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assign lock = tmp4 == 64'h5443474D489DFDD3;
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endmodule
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